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Volume Controller IC
PT2259
DESCRIPTION
PT2259 is an 8-pin 2-channel volume controller which utilizes CMOS technology and incorporates the I2C interface control. The controller features an attenuation range of 0 to -79dB, low noise output, a high degree of stereo separation and requires only a small number of external components. PT2259 is an essential component for modern audio visual systems.
FEATURES
* * * * * * * * Attenuation range: 0 to -79dB in 1dB steps Operating voltage: 4 to 9V Low power consumption Low signal noise: S/N > 100dB (A-weighting) Stereo separation > 100dB Requires few external components 2-channel volume individual adjust Available in 8 Pins DIP or SOP
APPLICATIONS
* * * * * Audio/visual surround sound systems Car audio systems Mini-compo systems Computer multi-media speakers Other audio applications
PT2259 V1.2
-1-
June, 2005
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
Volume Controller IC
PT2259
BLOCK DIAGRAM
PT2259 V1.2
-2-
June, 2005
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Volume Controller IC
PT2259
PIN CONFIGURATION
LIN LOUT VSS SDA 1 2 3 4 PT2259 8 7 6 5 RIN ROUT VDD SCL
PIN DESCRIPTION
Pin Name
LIN LOUT VSS SDA SCL VDD ROUT RIN
I/O
I O I I O I
Description Left Channel Input (capacitor coupled to input port) Left Channel Output (capacitor coupled to output port) Ground I2C Data Input I2C Clock Input Power Supply Right Channel Output (capacitor coupled to input port) Right Input Channel (capacitor coupled to output port)
Pin No.
1 2 3 4 5 6 7 8
PT2259 V1.2
-3-
June, 2005
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Volume Controller IC
PT2259
FUNCTIONAL DESCRIPTION
I2C BUS INTERFACE
In PT2259 the DATA and CLK make up the bus interface through which data is transmitted to and from the microprocessor.
DATA VALIDITY
Data on the DATA line is considered valid and stable only when the CLK signal is in the "high" state. In addition, the "high" and "low" states of the DATA line can change only when the CLK signal is in the "low" state. Please refer to the diagram below:
START AND STOP CONDITIONS
A start condition is activated when: 1. the CLK signal is set to "high", and 2. the DATA signal shifts from "high" to "low" A stop condition is activated when: 1. the CLK signal is set to "high", and 2. the DATA signal shifts from "low" to "high" Please refer to the timing diagram below:
PT2259 V1.2
-4-
June, 2005
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Volume Controller IC
PT2259
BYTE FORMAT
Every byte transmitted to the DATA line consists of 8 bits and each byte must be followed by an "acknowledge" bit. The MSB is transmitted first.
ACKNOWLEDGE SIGNAL
During the ninth clock pulse, the microprocessor puts a resistive "high" level on the DATA line. If the peripheral audio processor (PT2259) acknowledges, it will pull the DATA line from a "high" state to a "low" state during this acknowledge clock phase so that the DATA line is in a stable "low" state during this clock pulse. Please refer to the diagram below.
The audio processor that has been address (PT2259) must generate an "acknowledge" signal after receiving each byte or the DATA line will remain at the "high" level during the ninth clock pulse.
TRANSMISSION WITHOUT ACKNOWLEDGE
If you do not wish the audio processor (PT2259) to detect the "acknowledge" signal, a simpler microprocessor transmission method can be used: after PT2259 has received a byte wait for one clock pulse and do not acknowledge it. If this approach is used, however, there is a greater chance for faulty operations to occur and noise immunity will be decreased.
PT2259 V1.2
-5-
June, 2005
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Volume Controller IC
PT2259
I2C START TIME
When PT2259 is powered on, a short period must elapse before voltage becomes stable. After the power is turned on, PT2259 must wait at least 200ms before it is able to send an I2C control signal otherwise control efficacy and normal operation will be comprised. Please refer to the diagram below:
V
POWER ON 90% VDD
VDD at least 200 mS
SDA/SCL
PT2259 V1.2
-6-
June, 2005
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Volume Controller IC
PT2259
INTERFACE PROTOCOL
The interface protocol consists of the following: 1. a start condition 2. the PT2259 address byte followed by an "acknowledge" signal 3. a data sequence (n-bytes and an "acknowledge" signal) 4. a stop condition Please refer to the following diagram:
Note: ACK=ACKNOWLEDGE Max Clock Speed = 100K BITS/S
SOFTWARE SPECIFICATIONS
PT2259 address is shown below: 1 MSB 0 0 0 1 0 0 0 LSB
PT2259 V1.2
-7-
June, 2005
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Volume Controller IC
PT2259
DATA BYTES DESCRIPTION
FUNCTION BITS
MSB 1 1 1 1 0 0 1 0
1 1 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 A3 0 A3 0 A3 0 0 0 A2 B2 A2 B2 A2 B2 0 1 A1 B1 A1 B1 A1 B1 0 C1
LSB A0 B0 A0 B0 A0 B0 0 C0
Function 2-channel, -1dB/step 2-channel, -10db/step Left channel, -1db/step Left channel, -10dB/step Right channel, -1dB/step Right channel, -10dB/step Clear register Mute select
ATTENUATION UNIT BITS
A3 0 0 0 0 0 0 0 0 1 1 A2/B2 0 0 0 0 1 1 1 1 0 0 A1/B1 0 0 1 1 0 0 1 1 0 0 A0/B0 0 1 0 1 0 1 0 1 0 1 Attenuation (dB) 0/0 -1/-10 -2/-20 -3/-30 -4/-40 -5/-50 -6/-60 -7/-70 -8/ -9/
MUTE FUNCTION BITS
C1 0 0 1 1 C0 0 1 0 1 Function
Mute OFF Right channel mute ON Left channel mute ON Left and right channel mute ON
PT2259 V1.2
-8-
June, 2005
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Volume Controller IC
PT2259
PT2259 CONTROL SOFTWARE PROCEDURE
PT2259 has a built-in Power-On Reset function which clears the function register to zero after power-on. In order to ensure normal operation under any operating voltage, it is recommended an instruction to clear the register must be transmitted. Please refer to the following diagram: Start 1 0 0 0 1 0 0 0 ACK 1 1 1 1 0 0 0 0 ACK Stop 2259 Address Clear Registry The PT2259 function register does not have any default settings. After clearing the register, an initial value must send in order to each register. If a register does has not been set, it is possible that no sound will be output. When adjusting the volume of PT2259, it is necessary to send a multiple of 10dB followed by a 1dB code to the attenuator in sequence. If this sequence is not followed, or if only a 10dB or 1dB value is sent, the IC may not operate normally. Please refer to the diagram below: Example : Request volume setting of -42dB: Start 1 0 0 0 1 0 0 0 ACK 1 1 1 0 0 1 0 0 ACK 1 1 0 1 0 0 1 0 ACK Stop 2259 Address -40dB -2dB Start 1 0 0 0 1 0 0 0 ACK 1 1 0 1 0 0 1 0 ACK 1 1 1 0 0 1 0 0 ACK Stop 2259Address -2dB -40dB The two methods above are both acceptable.
WARNING! THE FOLLOWING TRANSMISSION METHODS ARE NOT PERMITTED.
Sending only a 10dB attenuation value: Start 1 0 0 0 1 0 0 0 ACK 1 1 1 0 0 1 0 0 ACK Stop 2259 Address -40dB Sending only a 1dB attenuation value: Start 1 0 0 0 1 0 0 0 ACK 1 1 0 1 0 0 1 0 ACK Stop 2259 Address -2dB Sending a 10dB code with a 1dB code simultaneously or in combination with other control codes: Start 1 0 0 0 1 0 0 0 ACK 1 1 0 1 0 0 1 0 ACK 0 0 1 0 0 0 1 0 ACK 1 1 1 0 0 1 0 0 ACK Stop 2259 Address -2dB Right Channel -2dB -40dB
PT2259 V1.2
-9-
June, 2005
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Volume Controller IC
PT2259
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Operating Temperature Storage Temperature Input Voltage Symbol Vcc Topr Tstg Vi Rating 12 -40 ~ +85 -65 ~ +150 -0.3 ~ Vcc + 0.3 Unit V C C V
ELECTRICAL CHARACTERISTICS
(Conditions: Vcc=9V, Vi=1Vrms, f=1kHz, Temp=27C)
Parameter Operating Voltage Operating Current Volume Attenuation Range Attenuation Step Attenuation Step Gain Error Interchannel Attenuation Gain Error
Maximum Output Voltage Total Harmonic Distortion Noise Output Signal-to-Noise Ratio Channel Separation Mute Frequency Response Input Impedance Output Impedance
Symbol Vcc Icc
ARANGE ASTEP GERR CERR Vomax
Testing Conditions
Vcc=9V, Vi=0V Minimum attenuation Maximum attenuation Vcc=9V, freq=1kHz, Volume Att.=0dB, Rload=50K, THD<1% f=1kHz, Vout=2Vrms Vol.Att.=0dB, Vout= A-weight Rload 200mVrms = 50 K Vin=GND, Mute=OFF, Volume Att = 0dB, A-weighted No-weighted Vin=1Vrms, Att.=0dB A-weighted Vin=2.5Vrms, freq.=1kHz, Volume Att.=0dB Vin=2.5Vrms, freq.=1kHz, Vol. Att.=0dB, A-weighted Vin=1Vrms, Volume Att.=-10dB f = 1kHz f=1kHz, Vout=100mVrms
Min. 4 2.0 95 110 100 90 -
Typ. 9 2.5 0 -79 1
0.5 0.5 2.3 0.07
Max. 12 3 2.5 0.09
Unit V mA
dB dB dB dB Vrms
THD NO SNR CS MUTE FR Rin Rout
0.003 0.005 2 100 120 120 95 1 33 6 3 103 125 125 97 1.3 -
% Vrms dB dB dB MHz K
PT2259 V1.2
- 10 -
June, 2005
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Volume Controller IC
PT2259
I2C BUS SECTION ELECTRICAL CHARACTERISTICS
Symbol
VIH VIL
Parameter Bus High Input Level Bus Low Input Level
Condition
-
Min.
3.5 -
Typ.
-
Max.
0.8
Unit
V V
PT2259 V1.2
- 11 -
June, 2005
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
Volume Controller IC
PT2259
PT2259 THD - FAST FOURIER TRANSFORM (FFT) ANALYSIS 1
(Conditions: Rload = 10K, Volume Att = 0dB, Vcc = 9V, Output Level = 1Vrms)
+0 -20 -40 -60
dB
-80 -100 -120 -140 -160 20 50 100 200 500 Hz 1k 2k 5k 10k
PT2259 THD - FAST FOURIER TRANSFORM (FFT) ANALYSIS 2
(Conditions: Rload = 10K, Volume Att = 0dB, Vcc = 9V, Output Level = 200m Vrms )
+0 -20 -40 -60
dB
-80 -100 -120 -140 -160 20 50 100 200 500 Hz 1k 2k 5k 10k
PT2259 V1.2
- 12 -
June, 2005
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Volume Controller IC
PT2259
PT2259 NOISE FLOOR - FAST FOURIER TRANSFORM (FFT) ANALYSIS 3
(Conditions: Rload = 10K, Volume Att = 0dB, Vcc = 9V, Vin=GND)
+0 -20 -40 -60
dB
-80 -100 -120 -140 -160 20
50
100
200
500 Hz
1k
2k
5k
10k
PT2259 THD VS. OUTPUT LEVEL
(Conditions: Rload = 10K, Volume Att = 0dB, Vcc = 9V, f = 1kHz A-weighted)
20 5 1
%
0.1 0.01 0.001 1m
2m
5m
10m
20m
50m Vrms
100m
200m
500m
1
2
4
PT2259 V1.2
- 13 -
June, 2005
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Volume Controller IC
PT2259
PT2259 THD VS. FREQUENCY RESPONSE AT VARIOUS OUTPUT LEVELS
(Conditions: Rload = 10K, Volume Att = 0dB, No-weighted) Vout=2.5 Vrms
1
%
0.1 0.01
Vout=1Vrms
0.001 20
Vout=200m Vrms
50
100
200
500 Hz
1k
2k
5k
10k
20k
Note: from top to bottom: Vout = 2.5Vrms, 1Vrms = 200mVrms
PT2259 INTERCHANNEL CROSSTALK
(Conditions: Rload = 10K, Volume Att = 0dB)
+0 -50
dB
-100 -150 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
PT2259 V1.2
- 14 -
June, 2005
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Volume Controller IC
PT2259
APPLICATION CIRCUIT
10uf IN-L OUT-L
1
10uf LIN LOUT VSS SDA RIN ROUT VDD SCL
8
IN-R OUT-R 5V-9V DC
10uf
2 3 4
10uf
7 6 5
0.1uf
47uf
PT2259 I 2 C Bus
MCU
PT2259 V1.2
- 15 -
June, 2005
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Volume Controller IC
PT2259
ORDERING INFORMATION
Valid Part Number PT2259 PT2259-S PT2259 (L) PT2259-S (L) Package Type 8-Pins, DIP, 300mil 8-Pins, SOP, 150mil 8-Pins, DIP, 300mil 8-Pins, SOP, 150mil Top Code PT2259 PT2259-S PT2259 PT2259-S
Notes: 1. (L), (C) or (S) = Lead Free 2. The Lead Free mark is put in front of the date code.
PT2259 V1.2
- 16 -
June, 2005
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Volume Controller IC
PT2259
PACKAGING INFORMATION
8-PIN, DIP, 300 MIL
PT2259 V1.2
- 17 -
June, 2005
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Volume Controller IC
Symbol A A1 A2 b b1 b2 b3 c c1 D D1 E E1 e eA eB eC L Min. 0.015 0.115 0.014 0.014 0.045 0.030 0.008 0.008 0.355 0.005 0.300 0.240
0.000 0.115
PT2259
Nom. 0.130 0.018 0.018 0.060 0.039 0.010 0.010 0.365 0.310 0.250 0.100 bsc. 0.300 bsc. 0.130 Max. 0.210 0.195 0.022 0.020 0.070 0.045 0.014 0.011 0.400 0.325 0.280
0.430 0.060 0.150
Notes: 1. Controlling Dimensions: INCHES. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension A, A1 and L are measured with the package seated in JEDEC Seating Plane Gauge GS-3. 4. E and eA measured with the leads constrained to be perpendicular to data -c- . 5. eB and eC are measured at the lead tips with the leads unconstrained. 6. Pointed or rounded lead tips are preferred to ease insertion. 7. b2 and b3 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm) 8. Distance between the leads including dambar protrusions to be 0.005 inch minimum. 9. Refer to JEDEC MS-001, Variation BA. JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.
PT2259 V1.2
- 18 -
June, 2005
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
Volume Controller IC
PT2259
8-PIN, SOP, 150 MIL
PT2259 V1.2
- 19 -
June, 2005
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
Volume Controller IC
PT2259
PT2259 V1.2
- 20 -
June, 2005
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Volume Controller IC
Symbol A A1 A2 b b1 c c1 D E E1 e L L1 L2 R R1 h 1 2 Min. 1.35 0.10 1.25 0.31 0.28 0.17 0.17 Typ. 4.90 BSC. 6.00 BSC. 3.90 BSC. 1.27 BSC. 1.04 REF. 0.25 BSC. -
PT2259
Max. 1.75 0.25 1.65 0.51 0.48 0.25 0.23
0.40 0.07 0.07 0.25 0 5 0
1.27 0.50 8 15 -
Note: 1. Dimensioning and tolerancing per ANSI Y 14.5M-1994 2. Controlling Dimension: MILLIMETERS. 3. Dimension D does not include mold flash protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm (0.006 in) per end. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25mm per side. D and E1 dimensions are determined at datum H. 4. The package top may be smaller than the package bottom. Dimensions D and E1 are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 5. Datums A & B to be determined at datum H. 6. N is the number of terminal positions. (N=8) 7. The dimensions apply to the flat section of the lead between 0.10 to 0.25mm from the lead tip. 8. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm total in excess of the "b" dimension at maximum material condition. The dambar cannot be located on the lower radius of the foot. 9. This chamfer feature is optional. If it is not present, then a pin 1 identifier must be located within the index area indicated. 10. Refer to JEDEC MS-012, Variation AA. JEDEC is the registered trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.
PT2259 V1.2 - 21 June, 2005

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